Decoupling capacitors have become necessary elements on VLSI (Very Large Scale Integration) chip designs with increased power dissipation and operating frequency. They provide the simple function of on-chip energy storage tanks for use when transient power requirements limit the immediate access to the normal power supply. That is, without decoupling capacitors (or, equivalently, a significant number/amount of decoupling capacitors), due to the inherent RLC properties and characteristics of the chip, chip package, board, power supply, etc., the reaction time of the power delivery system may not be fast enough to react to power demand. If, then, the power delivery system cannot react to the demand, a voltage drop occurs, which can have detrimental effects to the chip itself (e.g., circuit slow-down, memory state loss, etc.).
Decoupling capacitors, however, permit high power demands to pull necessary energy from their tanks, reducing or eliminating the voltage drop. The capacitors themselves are then recharged by the power supply at a secondary rate (the topic of time constants associated with the decoupling capacitor is complex and is not pertinent to the disclosure of the present invention).
Many methods have been devised to create the decoupling capacitors in standard VLSI processes. The most common method involves creating standard gate (thin) oxide over either a substrate or an n/p well, and tying the power supply voltages to either side of the thus created parallel plate capacitor. See, for example, U.S. Pat. Nos. 5,304,506, 5,394,294, and 5,329,237. This permits the decoupling capacitor to be created in a standard CMOS (complementary metal-oxide semiconductor) process with little or no mask addition or process complication.
However, complications do arise in the manufacture of such structures. Because they are made from gate (thin) oxide, they are subject to oxide shorts, perhaps the largest yield detractor in cutting-edge CMOS processes. And, because they consist of a large area of thin oxide, the probability of an oxide defect is highly increased. As a result, many of the created on-chip decoupling capacitors are defective and create shorts from the power supply to ground, causing increased power consumption, which then further aggravates the need for decoupling capacitors by increasing peak power demands. Note that such shorts may be large enough to cause the capacitor to become completely ineffective (and should be removed from the system) or small enough to create more chip stand-by current but still retaining a significant energy storage advantage. Note that in both cases the chip remains functional: an undesired decoupling capacitor does not affect the chip operation.
As a result, methods have been devised to selectively turn off or remove the decoupling capacitors from the system when such defects occur for both capacitor functionally and chip current purposes. That is, a non-functioning decoupling capacitor is unnecessary. Also, because most failures in such capacitors occur when the plates are resistively coupled and because the plates are necessarily connected to power and ground, such a non-functioning capacitor necessarily causes an unnecessary increase in chip power dissipation.
The most popular method for removing the decoupling capacitor from the system involves the addition of a fuse into the decoupling capacitor circuitry, as shown in FIG. 1. Referring to FIG. 1, as will be appreciated by those skilled in the art, a typical integrated circuit has a number of logic circuits, such as logic circuits 101 and 102, formed on a semiconductor substrate 10 by a sequence of well-known process steps. Each logic circuit 101, 102 is connected to an appropriate voltage source V+ also located on the semiconductor substrate 10. A decoupling capacitor 105, 106 couples the voltage source V+ to a suitable common or "ground" terminal so that any sharp fluctuations in the voltage (i.e., bounce) of the voltage source V+ are shunted through the decoupling capacitor 105, 106 to ground. In this manner, the decoupling capacitor 105, 106 isolates the logic circuit 101, 102 from rapid changes in power supply voltages.
Removal of the decoupling capacitor 105, 106 involves blowing the fuse 103, 104. Note, the physical arrangement of the fuse with respect to the decoupling capacitor can be reversed so that a terminal of the fuse is coupled to ground. In either embodiment, the opening of the circuit by deleting the fuse link 103, 104 prevents current flow from the supply source V+ through the failing ("failing" means defective and leaking current through the parallel plate structure due to dielectric failure) capacitor 105, 106 to ground.
The fuse 103, 104 is traditionally constructed using a long thin metal line. When the capacitor 105, 106 becomes defective, electromigration effects based on the unidirectional flow to ground force the atoms in the metal wire to move (migrate), which over time creates an open. Such effects may take minutes, hours, or even years to "blow" the fuse 103, 104.
This, creates a dilemma in the circuit based on the time involved for the fuse 103, 104 to blow (open). That is, if the resistor coupled between the capacitor plates is large (indicating a smaller, but still important, defect), then the current between the plates and the fuse is small, which means the electromigration-blown fuse will take a long time to open. Thus, small defects, although they degrade or negate the capacitor's effectiveness, will take a long time to demonstrate themselves in the removal of the associated decoupling capacitor 105, 106.
Therefore, there is a need in the art for an improved system for blowing a fuse coupled to a decoupling capacitor.